1. Field of the Invention
This invention relates to a semiconductor memory device, and more especially to a data read method of an EEPROM, which has electrically rewritable and non-volatile memory cells arranged therein.
2. Description of Related Art
An EEPROM (Electrically Erasable and Programmable Read-Only-Memory) is usually formed of memory cells with such a transistor structure that a charge storage layer (usually, floating gate) and a control gate are stacked. This memory cell stores a threshold voltage state, which is defined by a charge storage state of the floating gate, as data in a non-volatile manner. For example, the memory cell stores binary data of a logic “0” data defined by a high threshold voltage state as a result of that electrons have been injected into the floating gate; or a logic “1” data defined by a low threshold voltage state as a result of that electrons in the floating gate have been released.
Finely chop the memory cell's threshold voltage, and it is possible to store multi-value data. For example, four-value data is stored as defined by two bits stored in one memory cell.
In various EEPROMs, there is known a NAND-type flash memory, which may be highly integrated because plural memory cells are so connected in series as to constitute a NAND cell unit. Both ends of the NAND cell unit are coupled to a bit line and a common source line via select gate transistors, respectively. Control gates in the NAND cell unit are coupled to different word lines from each other.
In the NAND-type flash memory, a set of memory cells arranged along a word line constitutes a page (or two pages). Data read or write of the NAND-type flash memory may be performed at substantially high rate because it is performed by a page.
In a read mode of the NAND-type flash memory, a read current, which is carried through a NAND-cell unit in accordance with data of a selected memory cell, is detected under the condition of: a read voltage is applied to a selected word line so that memory cells become on or off based on data thereof; a pass voltage to non-selected (i.e., unselected) word lines so that memory cells turn on without regard to data thereof; and select gate transistors are turned on.
As a sense amplifier for reading data, any method of current-detecting type and voltage-detecting type may be used. In case, for example, a voltage-detecting type sense amplifier is used, a bit line is precharged to a certain voltage, and then set in a floating state. Thereafter, the bit line is subjected to discharge via a NAND cell unit. The sense amplifier detects the bit line voltage, which is different due to data of a selected memory cell, thereby judging data. In the data read mode, the common source line of the memory cell array is usually set at ground potential.
In case of binary data storage scheme, a relationship between read current (i.e., cell current), Icell, of a selected memory cell and control gate voltage (i.e., selected word line voltage) in the read mode is shown in FIG. 17. The sense amplifier detects in principle a deference between cell current Icell(1) of data “1” and cell current Icell(0) of data “0” on the condition of a read voltage Vr application. To prevent erroneous reading, it is required to set a lower limit value of the cell current Icell(1) and an upper limit value of the cell current Icell(0), and deal with a range between the lower limit value and upper limit value as a “forbidden range” or “inhibited range” as shown in FIG. 17.
This means, in other words, that it is required of the threshold voltage Vt, which defines the memory cell's data, to be set to have a certain inhibited range, INHV, therein as shown in FIG. 18.
On the other hand, as the memory cell is more and more miniaturized in the NAND-type flash memory, it has become impossible to disregard the short-channel effect. FIG. 19 shows the relationships between read current and control voltage of two memory cells A and B, the former having a large short-channel effect; and the latter a small short-channel effect. As shown in FIG. 19, the larger the short-channel effect, the less the dependence of the read current on the control voltage.
Therefore, the relationships between the read current Icell and the threshold voltage for the memory cells “A” and “B” are shown in FIG. 20. The inhibited range INHV(B) of the threshold voltage of memory cell “B” with a large short-channel effect is wider than the inhibited range INHV(A) of the threshold voltage of memory cell “A” with a small short-channel effect. This fact means that data read margin is reduced as the memory cell is more miniaturized.
So far, it has been explained a conventional read condition that the common source line is set at ground potential. By contrast, it has already been provided such a method that the common source line is set at a certain potential except ground potential under a certain read condition. For example, for the purpose of four-value data judging with two read operations, a method of controlling the source line has been provided (see, for example, Unexamined Japanese Patent Application Publication No. 2000-228092).
For reading data of an EEPROM, which stores four-value data designated as “xy” defined by an upper bit “x” and a lower bit “y”, it is usually performed three times read operations as follows: at a first timing, the upper bit “x” of the memory cells is detected; and at second and third timings, read operations will be done for judging the lower bit “y” for memory cells having the upper bits “x” of “0” and “1”, respectively. By contrast to this, to judge the four-value data with two read operations, the source line voltage is controlled as follows: at a first timing, upper bit data read is performed; and at a second timing of lower bit data reading, a certain read voltage is applied to memory cells under such the condition of: with respect to memory cell(s), upper bit of which is “1” (i.e., a low threshold voltage state), the source line voltage is set at 0V, while with respect to memory cell(s), upper bit of which is “0” (i.e., a high threshold voltage state), the source line is applied with a positive voltage so as to apparently boost the threshold voltage. As s result, the lower bit data may be judged with one read operation without regard to the upper bit data.
In the NAND-type EEPROM, the bias condition of the NAND cell unit at the write-verify read time is different from that at the erase-verify read time, and this results in that read currents (i.e., judging current) are different from each other. Considering it, there has been provided such a proposal that a positive voltage is applied to the source line at the erase-verify time, thereby making the judging currents of both of the write-verify operation and the erase-verify operation constant (see, Unexamined Japanese Patent Application Publication No. 2000-268585).